The explosion of generative artificial intelligence has forced the technology industry to rapidly revise its approach to energy efficiency. Responding to the growing demand of data centres that are choking on excess information processing, Samsung’s research department has unveiled a technology that could drastically change the economics of storage. The new generation of NAND flash memory promises to reduce energy consumption during read and write operations by up to 96 per cent compared to current market standards.
The Korean giant’s engineers have moved away from traditional oxide semiconductors to ferroelectric transistors. Although this technology has so far been overlooked in high-power circuits due to its high threshold voltage, Samsung has managed to turn this apparent disadvantage into a key architectural advantage. In modern 3D NAND structures, where cells are connected in series, precise control of leakage currents is critical to chip stability. The new solution effectively blocks the flow of current below a certain threshold, eliminating energy losses that have previously increased exponentially as more layers of memory are added.
The implications of this discovery go beyond the chip architecture itself. With the current race for the number of layers in storage, ferroelectrics could become the standard to further scale capacity without crippling power costs. Although the technology will first go into server and enterprise applications, in the long term it will also define the mobile and wearables market. However, cautious optimism should be exercised – the mass production schedule remains in the realm of corporate plans for the time being, and consumer deployments will still have to wait for the market.
